1. Field of the Invention
The present invention relates to plate voltage generation circuits. In detail, the present invention relates to a plate voltage generation circuit capable of setting a dead band in an output voltage when an output circuit generates the output voltage, that is half an external power supply voltage VDD. Particularly, the present invention relates to a plate voltage generation circuit capable of changing the width of a dead band into an arbitrary different value.
2. Description of the Related Art
Controlling a dead band in the above-mentioned kind of plate voltage generation circuit is used in order to suppress a through current in a push-pull output circuit. The push-pull output circuit is provided for a circuit for generating a voltage used as a cell plate voltage of a cell capacitor and a voltage used as a precharge voltage for a bit line.
A plurality of techniques for suppressing such a through current are known. According to those techniques, however, a dead band is set in order to always restrict the through current, generated in an output circuit, to a predetermined value or lower. The through current is generated when the dead band disappears due to manufacturing variations.
In the known dead-band control, as compared with an operating current of the order of milliamperes (mA), the through current differs from the operating current by an order of amplitude. That is, the through current is negligible in chip operation. Further controlling the through current interferes with stabilization of voltage level supplied to the above plate voltage generation circuit. From this viewpoint, the dead band is not widened more than necessary. When a refresh current of 1 to 3 mA, which is conventionally set, is reduced to 100 μA or lower in order to achieve ultra-low current consumption, however, the through current becomes a problem. For example, a dynamic random access memory (DRAM) requires refresh operation to hold written data. The refresh operation means that data is again read from the memory within refresh time serving as the maximum data hold time and is then rewritten.
Referring to FIG. 1, for example, the refresh time is the sum of refresh operation time T1 and data hold time T2. A refresh current is obtained by an expression of (I1·T1+I2·T2)/(T1+T2), where I1 denotes operating current upon rewriting, T1 denotes rewrite time, I2 denotes standby current for data hold time, and T2 denotes the data hold time.
The refresh current can be reduced by extending the data hold time using a process improvement and a circuit technique such as a data correction technique. Extending the data hold time results in an increase in proportion of the time T2 in FIG. 1. As a result, the through current of several tens of μA in the current I2 is not negligible. When the width of the dead band is wider than the conventional one in order to reduce the through current of several tens of μA generated in the data hold operation, however, response speed of the push-pull output circuit decreases. Disadvantageously, a voltage level becomes unstable. With the above points as background, we consider voltage generation circuits capable of suppressing a very small through current in the data hold operation without deteriorating the characteristics of the known voltage generation circuit. Then, the present invention is realized.
Japanese Unexamined Patent Application Publication No. 6-338188 (hereinbelow, referred to as Document 1) discloses an example of this kind of voltage generation circuit. In this voltage generation circuit, a through current can be reduced in an output buffer circuit serving as a push-pull output circuit. Further, the width of a dead band of an output voltage can be freely set. The voltage generation circuit can also be applied to devices with an SOI (silicon-on-insulator) structure.
Referring to FIG. 2, the voltage generation circuit includes a reference potential (or voltage) generation circuit 111, a pair of shift circuits 112a and 112b, and an output buffer circuit 113. The reference potential generation circuit 111 includes resistors R11, R12, and R13 to generate two different reference potentials (voltages). The pair of shift circuits 112a and 112b shift the two reference potentials by a predetermined level, respectively. The shift circuit 112a has transistors Q11, Q12, Q13, and Q14. The shift circuit 112b has transistors Q15, Q16, Q17, and Q18. The output buffer circuit 113 includes a pair of source follower transistors (hereinbelow, simply referred to as transistors) Q19 and Q20 having opposite conductivities. Voltages shifted by the pair of shift circuits 112a and 112b are applied to the respective gates of the transistors Q19 and Q20.
A power supply voltage as an external power supply voltage is designated by reference symbol VCC. In the reference potential generation circuit 111, the resistances of the resistors R11, R12, and R13 are set properly. The reference potential generation circuit 111 generates two reference potentials [(VCC/2)+ΔV] and [(VCC/2)−ΔV]. The two reference potentials are shifted by the pair of shift circuits 112a and 112b, respectively. The output buffer circuit 113 receives the shifted voltages and generates an output voltage of VCC/2.
In this voltage generation circuit, the dead band can be set around VCC/2 in the output voltage. Thus, the through current does not flow in a series circuit composed of the transistors Q19 and Q20. When the respective resistances of the resistors R11, R12, and R13 to produce two reference potentials are varied in the reference potential generation circuit 111, the width of the dead band can be freely controlled.
Document 1 also discloses an example in which the drive capability of an output buffer circuit component can be changed in two levels corresponding to output voltages. FIG. 3 shows the structure of a voltage generation circuit according to this example.
Referring to FIG. 3, the voltage generation circuit has a reference potential generation circuit 121, four shift circuits 112a, 112b, 122a, and 122b, and two output buffer circuits 113 and 123 having different drive capabilities. In the reference potential generation circuit 121, two resistors R21 and R22 are connected to both the ends of the series circuit composed of the three resistors R11, R12, and R13. The resistors R11 to R13 are included in the reference potential generation circuit 111 in FIG. 2. Thus, the reference potential generation circuit 121 generates four reference potentials. The four reference potentials are shifted by the shift circuits 112a, 112b, 122a, and 122b, respectively. The shifted voltages are applied to the two output buffer circuits 113 and 123, respectively. The two output buffer circuits 113 and 123 generate different output voltages.
Document 1 also explains that the drive capability of the output buffer circuit component can be changed in three levels or more, namely, in multi-levels corresponding to the output voltages. This multi-level output voltages are realized by generating three or more reference potentials and arranging a plurality of shift circuits and output buffer circuits so as to correspond to those reference potentials.
The above-mentioned voltage generation circuits have the following disadvantages.
In the voltage generation circuits, the dead band is set using two or more reference voltages (potentials). A plurality of dead bands can also be set. However, since the circuitry of each voltage generation circuit itself is fixed, the width of each dead band cannot be changed at will in chip operation. To freely change the width of each dead band in accordance with the chip operation, therefore, the reference potentials have to be changed. Accordingly, the value of the power supply voltage VCC has to be changed. If the power supply voltage VCC is not changed, the resistances of the respective resistors for generating a plurality of reference potentials have to be changed. However, since the arranged resistors are not variable resistors, their resistances cannot be changed depending on the chip operation. Consequently, the width of each dead band cannot be freely controlled during the chip operation.
Further, the voltage generation circuit in FIG. 3 has such a structure that the two resistors, two shift circuits, and one output buffer circuit are added to the components of the voltage generation circuit in FIG. 2. That is, this voltage generation circuit has many components. Disadvantageously, the layout area thereof increases.